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| RTL8169SB(L) INTEGRATED GIGABIT ETHERNET CONTROLLER (NIC) DATASHEET Rev. 1.5 10 August 2004 Track ID: JATR-1076-21 RTL8169SB(L) Datasheet COPYRIGHT (c)2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT This document is intended for use by the software engineer when programming for Realtek RTL8169SB(L) controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision 1.0 1.1 Release Date 2003/11/17 2004/01/28 Summary First release. EEDI/AUX and EEDO description changed in Table 3, page 7. Pin 11 changed from NC to VSS (see Table 8, page 9). Pin 12 changed from NC to AVDDH (see Table 8, page 9). Add CardBus, Boot ROM function related content (see Table 1, page 4). Revised VDD25 parameters (see Table 12, page 26, and Table 15, page 27). Corrected `VDD25' pin name to `AVDDL'. Revised AVDDL parameters (see Table 12, page 26, and Table 15, page 27). Revised Pin 126 (VDD12A) description (see Table 8, page 9, Table 11, page 26, Table 12, page 26, and Table 15, page 27). 1.2 1.3 1.4 1.5 2004/04/16 2004/07/09 2004/07/26 2004/08/10 Integrated Gigabit Ethernet Controller (NIC) ii Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet Table of Contents 1. 2. 3. 4. 5. GENERAL DESCRIPTION................................................................................................................................................1 FEATURES...........................................................................................................................................................................2 SYSTEM APPLICATIONS .................................................................................................................................................2 PIN ASSIGNMENTS ...........................................................................................................................................................3 PIN DESCRIPTIONS ..........................................................................................................................................................4 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 6. POWER MANAGEMENT/ISOLATION...............................................................................................................................4 PCI INTERFACE ............................................................................................................................................................5 EEPROM ....................................................................................................................................................................7 TRANSCEIVER INTERFACE ............................................................................................................................................7 CLOCK .........................................................................................................................................................................8 REGULATOR & REFERENCE..........................................................................................................................................8 LEDS ...........................................................................................................................................................................8 POWER & GROUND ......................................................................................................................................................9 NC (NOT CONNECTED) PINS........................................................................................................................................9 FUNCTIONAL DESCRIPTION.......................................................................................................................................10 6.1. 6.1.1. 6.1.2. 6.1.3. 6.1.4. 6.2. 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5. PCI BUS INTERFACE ..................................................................................................................................................10 Byte Ordering .......................................................................................................................................................10 Interrupt Control .................................................................................................................................................. 11 Latency Timer ....................................................................................................................................................... 11 64-Bit Addressing ................................................................................................................................................. 11 PCI BUS OPERATION..................................................................................................................................................12 Target Read...........................................................................................................................................................12 Target Write ..........................................................................................................................................................13 Master Read .........................................................................................................................................................14 Master Write .........................................................................................................................................................15 Configuration Access............................................................................................................................................16 Integrated Gigabit Ethernet Controller (NIC) iii Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.3. 6.3.1. 6.3.2. 6.3.3. 6.3.4. 6.3.5. 6.4. 6.4.1. 6.4.2. 6.5. 6.6. 6.7. 7. LED FUNCTIONS........................................................................................................................................................17 Link Monitor.........................................................................................................................................................17 Rx LED .................................................................................................................................................................17 Tx LED .................................................................................................................................................................18 Tx/Rx LED ............................................................................................................................................................19 LINK/ACT LED ....................................................................................................................................................20 PHY TRANSCEIVER....................................................................................................................................................21 PHY Transmitter ...................................................................................................................................................21 PHY Receiver........................................................................................................................................................21 NEXT PAGE ................................................................................................................................................................22 EEPROM INTERFACE ................................................................................................................................................22 POWER MANAGEMENT...............................................................................................................................................23 CHARACTERISTICS .......................................................................................................................................................26 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.6.1. 7.7. 7.7.1. 7.7.2. 7.7.3. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................26 RECOMMENDED OPERATING CONDITIONS .................................................................................................................26 CRYSTAL REQUIREMENTS ..........................................................................................................................................26 THERMAL CHARACTERISTICS.....................................................................................................................................27 DC CHARACTERISTICS...............................................................................................................................................27 AC CHARACTERISTICS...............................................................................................................................................28 Serial EEPROM Interface Timing ........................................................................................................................28 PCI BUS OPERATION TIMING .....................................................................................................................................29 PCI Bus Timing Parameters .................................................................................................................................29 PCI Clock Specification .......................................................................................................................................31 PCI Transactions ..................................................................................................................................................32 8. MECHANICAL DIMENSIONS .......................................................................................................................................39 8.1. 8.2. 8.3. 8.4. 128-PIN QFP MECHANICAL DIMENSIONS ..................................................................................................................39 NOTES FOR 128-PIN QFP DIMENSIONS ......................................................................................................................40 128-PIN LQFP MECHANICAL DIMENSIONS................................................................................................................41 NOTES FOR 128-PIN LQFP DIMENSIONS....................................................................................................................42 9. ORDERING INFORMATION..........................................................................................................................................43 Integrated Gigabit Ethernet Controller (NIC) iv Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet List of Tables TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. TABLE 9. POWER MANAGEMENT/ISOLATION ..............................................................................................................................4 PCI INTERFACE ...........................................................................................................................................................5 EEPROM ....................................................................................................................................................................7 TRANSCEIVER INTERFACE............................................................................................................................................7 CLOCK .........................................................................................................................................................................8 REGULATOR & REFERENCE .........................................................................................................................................8 LEDS...........................................................................................................................................................................8 POWER & GROUND......................................................................................................................................................9 NC (NOT CONNECTED) PINS .......................................................................................................................................9 TABLE 10. EEPROM INTERFACE ...............................................................................................................................................22 TABLE 11. ABSOLUTE MAXIMUM RATINGS................................................................................................................................26 TABLE 12. RECOMMENDED OPERATING CONDITIONS.................................................................................................................26 TABLE 13. CRYSTAL REQUIREMENTS .........................................................................................................................................26 TABLE 14. THERMAL CHARACTERISTICS ....................................................................................................................................27 TABLE 15. DC CHARACTERISTICS ..............................................................................................................................................27 TABLE 16. EEPROM ACCESS TIMING PARAMETERS .................................................................................................................28 TABLE 17. PCI BUS TIMING PARAMETERS .................................................................................................................................29 TABLE 18. MEASUREMENT CONDITION PARAMETERS ................................................................................................................30 TABLE 19. CLOCK AND RESET SPECIFICATIONS..........................................................................................................................31 TABLE 20. ORDERING INFORMATION..........................................................................................................................................43 Integrated Gigabit Ethernet Controller (NIC) v Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet List of Figures FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. RTL8169SB(L) 128-PIN (L)QFP PIN ASSIGNMENTS.................................................................................................3 LITTLE-ENDIAN BYTE ORDERING.............................................................................................................................10 BIG-ENDIAN BYTE ORDERING..................................................................................................................................11 TARGET READ OPERATION.......................................................................................................................................12 TARGET WRITE OPERATION .....................................................................................................................................13 MASTER READ OPERATION ......................................................................................................................................14 MASTER WRITE OPERATION.....................................................................................................................................15 RX LED....................................................................................................................................................................17 TX LED ....................................................................................................................................................................18 FIGURE 10. TX/RX LED..............................................................................................................................................................19 FIGURE 11. LINK/ACT LED......................................................................................................................................................20 FIGURE 12. SERIAL EEPROM INTERFACE TIMING.....................................................................................................................28 FIGURE 13. OUTPUT TIMING MEASUREMENT CONDITIONS.........................................................................................................30 FIGURE 14. INPUT TIMING MEASUREMENT CONDITIONS ............................................................................................................30 FIGURE 15. 3.3V CLOCK WAVEFORM.........................................................................................................................................31 FIGURE 16. CLOCK SKEW DIAGRAM...........................................................................................................................................31 FIGURE 17. I/O READ .................................................................................................................................................................32 FIGURE 18. I/O WRITE................................................................................................................................................................32 FIGURE 19. CONFIGURATION READ ............................................................................................................................................33 FIGURE 20. CONFIGURATION WRITE...........................................................................................................................................33 FIGURE 21. BUS ARBITRATION ...................................................................................................................................................34 FIGURE 22. MEMORY READ BELOW 4GB ...................................................................................................................................34 FIGURE 23. MEMORY WRITE BELOW 4GB .................................................................................................................................35 FIGURE 24. TARGET INITIATED TERMINATION - DISCONNECT....................................................................................................35 FIGURE 25. TARGET INITIATED TERMINATION - ABORT .............................................................................................................36 FIGURE 26. MASTER INITIATED TERMINATION - ABORT.............................................................................................................36 FIGURE 27. PARITY OPERATION - ONE EXAMPLE ......................................................................................................................37 FIGURE 28. MEMORY READ ABOVE 4GB (DAC) .......................................................................................................................38 FIGURE 29. MEMORY WRITE ABOVE 4GB (DAC)......................................................................................................................38 Integrated Gigabit Ethernet Controller (NIC) vi Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 1. General Description The Realtek RTL8169SB(L) NIC Gigabit Ethernet controllers (RTL8169SB (128-QFP) & RTL8169SBL (128-LQFP)) combine a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, 32-bit PCI bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, they offer high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The devices support the PCI v2.3 and CardBus (RTL8169SBL only) bus interfaces for host communications with power management, and comply with the IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. They also support an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. They support the Advanced Configuration Power management Interface (ACPI)--power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)--to achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also supported. In addition to the ACPI feature, the RTL8169SB(L) supports remote wake-up (including AMD Magic Packet, Re-LinkOk, and Microsoft(R) Wake-up frame) in both ACPI and APM (Advanced Power Management) environments. The LWAKE pin provides four different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality. To support WOL from a deep power down state (e.g. D3cold, i.e. main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8169SB(L). The RTL8169SB(L) is fully compliant with Microsoft(R) NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and supports IEEE 802 IP Layer 2 priority encoding and 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. Also, the devices boost their PCI performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To better qualify for server use, the RTL8169SB(L) support the PCI Dual Address Cycle (DAC) command when the assigned buffers reside at a physical memory address higher than 4 Gigabytes. Integrated Gigabit Ethernet Controller (NIC) 1 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 2. Features Integrated 10/100/1000 transceiver Auto-Negotiation with Next Page capability Supports PCI rev.2.3, 32-bit, 33/66MHz The RTL8169SBL supports CardBus mode. The CIS data can be stored in either EEPROM or expansion ROM Supports pair swap/polarity/skew correction Crossover Detection & Auto-Correction Wake-on-LAN and remote wake-up support Microsoft(R) NDIS5 Checksum Offload (IP, TCP, UDP) and largesend offload support Supports Full Duplex flow control (IEEE 802.3x) Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab Supports IEEE 802.1P Layer 2 Priority Encoding Supports IEEE 802.1Q VLAN tagging Serial EEPROM Supports up to 128Kbytes Boot ROM 3.3V signaling, 5V PCI I/O tolerant Transmit/Receive FIFO (8K/64K) support Supports power down/link down power saving Supports PCI Message Signaled Interrupt (MSI) 128-pin QFP package (RTL8169SB) and 128-pin LQFP package (RTL8169SBL) 3. System Applications Gigabit Ethernet Network Interface Card Gigabit Ethernet CardBus Card Integrated Gigabit Ethernet Controller (NIC) 2 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 4. Pin Assignments 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVDDL VSSPST GND ISOLATEB VDD12 INTAB VDD33 PCIRSTB PCICLK GNTB REQB PMEB VDD12 PCIAD31 PCIAD30 GND PCIAD29 PCIAD28 VSSPST 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MDI3MDI3+ VSS AVDDL MDI2MDI2+ VSS AVDDH VSS AVDDH VSS CTRL25 AVDDL MDI1MDI1+ VSS AVDDL MDI0MDI0+ 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PCIAD27 PCIAD26 VDD33 PCIAD25 PCIAD24 CBEB3 VDD12 IDSEL PCIAD23 GND PCIAD22 PCIAD21 VSSPST GND PCIAD20 VDD12 PCIAD19 VDD33 PCIAD18 PCIAD17 PCIAD16 CBEB2 FRAMEB GND IRDYB VDD12 RTL8169SB(L) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 VSS RSET VDD12A CTRL12 VSS VSS XTAL2 XTAL1 AVDDH VSSPST GND LED0 VDD12 LED1 LED2 LED3 GND EESK VDD12 EEDI EEDO VDD33 EECS LANWAKE/CSTSCHG PCIAD0 PCIAD1 65 CLKRUNB on SBL Version. NC on SB Ver. VSSPST 66 TRDYB 67 DEVSELB 68 STOPB 69 PERRB 70 VDD33 71 NC 72 GND 73 74 NC SERRB 75 PAR 76 CBEB1 77 78 VDD12 79 PCIAD15 80 GND VSSPST 81 82 PCIAD14 PCIAD13 83 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 PCIAD2 VSSPST GND VDD12 PCIAD3 PCIAD4 PCIAD5 PCIAD6 VDD33 PCIAD7 CBEB0 VSSPST PCIAD8 PCIAD9 M66EN PCIAD10 PCIAD11 PCIAD12 VDD33 Figure 1. RTL8169SB(L) 128-Pin (L)QFP Pin Assignments 3 Track ID: JATR-1076-21 Rev. 1.5 Integrated Gigabit Ethernet Controller (NIC) RTL8169SB(L) Datasheet 5. I: Input. Pin Descriptions The following signal type codes are used in the tables: O: Output. T/S: Tri-State bi-directional input/output pin. S/T/S: Sustained Tri-State. O/D: Open Drain. 5.1. Power Management/Isolation Table 1. Symbol PMEB (PME#) ISOLATEB (ISOLATE#) Type O/D Pin No 31 Power Management/Isolation Description Power Management Event: Open drain, active low. Used to request a change in the current power management state and/or to indicate that a power management event has occurred. Isolate Pin: Active low. Used to isolate the RTL8169SB(L) from the PCI bus. The RTL8169SB(L) will not drive its PCI outputs (excluding PME#) and will not sample its PCI input (including PCIRSTB and PCICLK) as long as the Isolate pin is asserted. LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This signal is used to inform the motherboard to execute the wake-up process. The motherboard must support Wake-On-LAN (WOL). There are 4 choices of output that may be asserted from the LANWAKE pin (active high, active low, positive pulse, and negative pulse). We can configure the LANWAKE output via two CONFIG bits: LWACT(Config1.4) and LWPTN(Config4.2). LWACT LWAKE Output 0 1 LWPTN 0 Active high Active low 1 Positive pulse Negative pulse The default output is an active high signal. Once a PME event is received, the LANWAKE and PMEB assert at the same time when the LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the LANWAKE asserts only when PMEB asserts and ISOLATEB is low. CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal is used by the RTL8169SBL in CardBus applications only and is used to inform the motherboard to execute the wake-up process whenever a PME event occurs. This is always an active high signal, and the setting of LWACT (bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4) is irrelevant in this case. I 23 LANWAKE/ CSTSCHG O 105 Integrated Gigabit Ethernet Controller (NIC) 4 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 5.2. PCI Interface Table 2. Symbol PCIADPIN31-0 Type T/S Pin No 33, 34, 36, 37, 39, 40, 42, 43, 47, 49, 50, 53, 55, 57, 58, 59, 79, 82, 83, 85, 86, 87, 89, 90, 93, 95, 96, 97, 98, 102, 103, 104 PCI Interface Description AD31-0: Low 32-bit PCI address and data multiplexed pins. The address phase is the first clock cycle in which FRAMEB is asserted. During the address phase, AD31-0 contains a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, it is a double-word address. The RTL8169SB(L) supports both big-endian and little-endian byte ordering. Write data is stable and valid when IRDYB is asserted. Read data is stable and valid when TRDYB is asserted. Data I is transferred during those clocks where both IRDYB and TRDYB are asserted. PCIADPIN31-24 are shared with Boot ROM data pins, while PCIADPIN16-0 are shared with Boot ROM address pins. CBEBPIN7-4 CBEBPIN3-0 PCICLK CLKRUNB on the RTL8169SBL NC on the RTL8169SB DEVSELB FRAMEB PCI bus command and Byte Enables multiplex pins. During the address phase of a transaction, CBEBPIN7-4 defines the bus command. During the data phase, CBEBPIN7-4 are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. CBEBPIN4 applies to byte 4, and CBEBPIN7 applies to byte 7. T/S 44, 60, 77, 92 PCI bus command and Byte Enables multiplex pins. During the address phase of a transaction, CBEBPIN3-0 defines the bus command. During the data phase, CBEBPIN3-0 are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. CBEBPIN0 applies to byte 0, and CBEBPIN3 applies to byte 3. I 28 PCI clock: This clock input provides timing for all PCI transactions and is input to the PCI device. Supports up to a 66MHz PCI clock. I/O 65 Clock Run: On the RTL8169SB this pin is Not Connected. This signal is used by the RTL8169SBL to request starting (or speeding up) of the PCICLK clock. CLKRUNB also indicates the clock status. For the RTL8169SBL, CLKRUNB is an open drain output as well as an input. The RTL8169SBL requests the central resource to start, speed up, or maintain the interface clock by the assertion of CLKRUNB. For the host system, it is an S/T/S signal. The host system (central resource) is responsible for maintaining CLKRUNB asserted, and for driving it high to the negated (deasserted) state. S/T/S 68 Device Select: As a bus master, the RTL8169SB(L) samples this signal to insure that a PCI target recognizes the destination address for the data transfer. As a target, the RTL8169SB(L) asserts this signal low when it recognizes its target address after FRAMEB is asserted. S/T/S 61 Cycle Frame: As a bus master, this pin indicates the beginning and duration of an access. FRAMEB is asserted low to indicate the start of a bus transaction. While FRAMEB is asserted, data transfer continues. When FRAMEB is de-asserted, the transaction is in the final data phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. T/S Integrated Gigabit Ethernet Controller (NIC) 5 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet Symbol GNTB Type I Pin No 29 Description Grant: This signal is asserted low to indicate to the RTL8169SB(L) that the central arbiter has granted the ownership of the bus to the RTL8169SB(L). This input is used when the device is acting as a bus master. Request: The RTL8169SB(L) will assert this signal low to request the ownership of the bus from the central arbiter. Initialization Device Select: This pin allows the device to identify when configuration read/write transactions are intended for it. Interrupt A: Used to request an interrupt. It is asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask. Initiator Ready: This indicates the initiating agent's ability to complete the current data phase of the transaction. As a bus master, this signal will be asserted low when the device is ready to complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. As a target, this signal indicates that the master has put data on the bus. Target Ready: This indicates the target agent's ability to complete the current phase of the transaction. As a bus master, this signal indicates that the target is ready for the data during write operations, or is ready to provide the data during read operations. As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYB signal. Data transaction takes place at the rising edge of CLK, when both IRDYB and TRDYB are asserted low. Parity: This signal indicates even parity across PCIADPIN31-0 and CBEB3-0 including the PAR pin. PAR is stable and valid one clock after each address phase. For data phase, PAR is stable and valid one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. As a bus master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. 66MHZ_ENABLE: This pin indicates to the device whether the bus segment is operating at 66 or 33MHz. When this pin (active high) is asserted, the current PCI bus segment that the device resides on operates in 66MHz mode. If this pin is de-asserted, the current PCI bus segment operates in 33MHz mode. Parity Error: This pin is used to report data parity errors during all PCI transactions except a Special Cycle. PERRB is driven active (low) two clocks after a data parity error is detected by the device receiving data, and the minimum duration of PERRB is one clock for each data phase with parity error detected. System Error: If an address parity error is detected and Configuration Space Status register bit 15 (detect parity error) is enabled, the device asserts the SERRB pin low and bit 14 of the Status register in Configuration Space. REQB IDSEL INTAB IRDYB T/S I O/D S/T/S 30 46 25 63 TRDYB S/T/S 67 PAR T/S 76 M66EN I 88 PERRB S/T/S 70 SERRB O/D 75 Integrated Gigabit Ethernet Controller (NIC) 6 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet Symbol STOPB PCIRSTB Type S/T/S I Pin No 69 27 Description Stop: Indicates that the current target is requesting the master to stop the current transaction. Reset: When PCIRSTB is asserted low, the device performs an internal system hardware reset. PCIRSTB must be held for a minimum period of 120ns. 5.3. EEPROM Table 3. Symbol EESK EEDI/AUX Type O O/I Pin No 111 109 EEPROM Description Serial data clock. EEDI: Output to serial data input pin of EEPROM AUX: Input pin to detect if Aux. Power exists or not on initial power-on. This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to aux. power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8169SB(L) assumes that no Aux. Power exists. Input from serial data output pin of EEPROM. EECS: EEPROM chip select. BROMCSB: This is the chip select signal of the Boot PROM. EEDO EECS/BROMCSB I O 108 106 5.4. Transceiver Interface Table 4. Symbol MDI[0]+ MDI[0]- MDI[1]+ MDI[1]- MDI[2]+ MDI[2]- MDI[3]+ MDI[3]- Type I/O I/O I/O I/O I/O I/O I/O I/O Pin No 1 2 5 6 14 15 18 19 Transceiver Interface Description In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX. In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. Integrated Gigabit Ethernet Controller (NIC) 7 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 5.5. Clock Table 5. Symbol Xtal1 Xtal2 Type I O Pin No 121 122 Clock Description Input of 25MHz clock reference. Output of 25MHz clock reference. 5.6. Regulator & Reference Table 6. Symbol CTRL25 CTRL12 RSET Type O O I Pin No 8 125 127 Regulator & Reference Description Regulator Control. Voltage control to external 2.5V regulator. Regulator Control. Voltage control to external 1.2V regulator. Reference. External Resistor Reference. 5.7. LEDs Table 7. Symbol LED0 LED1 LED2 LED3 Type O O O O Pin No 117 115 114 113 LEDS1-0 LED0 LED1 LED2 LED3 00 Tx/Rx LINK100 LINK10 LINK1000 LEDs Description 01 ACT(Tx/Rx) LINK10/100/ 1000 FULL 10 Tx LINK10/100 /1000 Rx FULL 11 LINK10/ ACT LINK100/ ACT FULL LINK1000/ ACT Note 1: LED0 is also BROMOEB to enable BROM's output buffer during BROM read operation. Note 2: During power down mode, the LED signals are logic high. Note 3: LEDS1-0's initial value comes from 93C46/93C56/93C66. Integrated Gigabit Ethernet Controller (NIC) 8 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 5.8. Power & Ground Table 8. Symbol VDD12A VDD12 Type Power Power Pin No 126 24, 32, 45, 54, 64, 78, 99, 110, 116 26, 41, 56, 71, 84, 94, 107 21, 22, 35, 38, 48, 51, 52, 62, 66, 73, 80, 81, 91, 100, 101, 112, 118, 119 3, 7, 16, 20 10, 12, 120 Power & Ground Description Analog 1.2V power supply. Digital 1.2V power supply. VDD33 GND/VSSPST Power Power Digital 3.3V power supply. Digital Ground. AVDDL AVDDH VSS Power Power Power Analog 2.5V power supply. Analog 3.3V power supply. 4, 9, 11, 13, 17, Analog Ground. 123, 124, 128 5.9. Symbol NC NC NC (Not Connected) Pins Table 9. Type Pin No 65 72, 74 NC (Not Connected) Pins Description Not Connected on RTL8169SB. CLKRUNB on RTL8169SBL. Not Connected. Integrated Gigabit Ethernet Controller (NIC) 9 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6. Functional Description 6.1. PCI Bus Interface The RTL8169SB(L) implements the PCI bus interface as defined in the PCI Local Bus Specifications Rev. 2.3. When internal registers are being accessed, the RTL8169SB(L) acts as a PCI target (slave mode). When accessing host memory for descriptor or packet data transfer, the RTL8169SB(L) acts as a PCI bus master. All of the required pins and functions are implemented in the RTL8169SB(L) as well as the optional pin, INTAB for support of interrupt requests. The bus interface supports 32-bit and 66MHz operation in addition to the more common 32-bit and 33MHz capabilities. For more information, refer to the PCI Local Bus Specifications Rev. 2.3, March 29, 2002. 6.1.1. Byte Ordering The RTL8169SB(L) can be configured to order the bytes of data on the PCI AD bus to conform to little-endian or big-endian ordering through the use of the ENDIAN bit of the C+ Command Register. When the RTL8169SB(L) is configured in big-endian mode, all the data in the data phase of either memory or I/O transaction to or from the RTL8169SB(L) is in big-endian mode. All data in the data phase of any PCI configuration transaction to RTL8169SB(L) should be little-endian, no matter whether the RTL8169SB(L) is set to big-endian or little-endian mode. When configured for little-endian (ENDIAN bit=0), the byte orientation for receive and transmit data and descriptors in system memory is as follows: 31 ~ 24 Byte 3 C/BE[3] (MSB) 23 ~ 16 Byte 2 C/BE[2] Figure 2. 15 ~ 8 Byte 1 C/BE[1] 7~0 Byte 0 C/BE[0] (LSB) Little-Endian Byte Ordering Integrated Gigabit Ethernet Controller (NIC) 10 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet When configured for big-endian mode (ENDIAN bit=1), the byte orientation for receive and transmit data and descriptors in system memory is as follows: 31 ~ 24 Byte 0 C/BE[3] (LSB) 23 ~ 16 Byte 1 C/BE[2] Figure 3. 15 ~ 8 Byte 2 C/BE[1] 7~0 Byte 3 C/BE[0] (MSB) Big-Endian Byte Ordering 6.1.2. Interrupt Control Interrupts are performed by asynchronously asserting the INTAB pin. This pin is an open drain output. The source of the interrupt can be determined by reading the Interrupt Status Register (ISR). One or more bits in the ISR will be set, denoting all currently pending interrupts. Writing 1 to any bit in the ISR register clears that bit. Masking of specific interrupts can be accomplished by using the Interrupt Mask Register (IMR). Assertion of INTAB can be prevented by clearing the Interrupt Enable bit in the Interrupt Mask Register. This allows the system to defer interrupt processing as needed. 6.1.3. Latency Timer The PCI Latency Timer described in LTR defines the maximum number of bus clocks that the device will hold the bus. Once the device gains control of the bus and issues FRAMEB, the Latency Timer will begin counting down. The LTR register specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8169SB(L). When the RTL8169SB(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8169SB(L) deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8169SB(L) initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write to LTR, and the default value is 00H. 6.1.4. 64-Bit Addressing The RTL8169SB(L) supports 64-bit addressing (Dual Address Cycle) as a bus master for transferring descriptor and packet data information. Dual Address Cycle (DAC) mode can be enabled or disabled through software. The RTL8169SB(L) only supports 32-bit addressing as a target. Integrated Gigabit Ethernet Controller (NIC) 11 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.2. PCI Bus Operation 6.2.1. Target Read A Target Read operation starts with the system generating FRAMEB, Address, and either an IO read (0010b) or Memory Read (0110b) command. If the 32-bit address on the address bus matches the IO address range specified in IOAR (for I/O reads) or the memory address range specified in MEM (for memory reads), the RTL8169SB(L) will generate DEVSELB 2 clock cycles later (medium speed). The system must tri-state the address bus, and convert the C/BE bus to byte enables after the address cycle. On the 2nd cycle after the assertion of DEVSELB, all 32-bits of data and TRDYB will become valid. If IRDYB is asserted at that time, TRDYB will be forced HIGH on the next clock for 1 cycle, and then tri-stated. If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8169SB(L) will still make data available as described above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted. Figure 4. Target Read Operation Integrated Gigabit Ethernet Controller (NIC) 12 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.2.2. Target Write A Target Write operation starts with the system generating FRAMEB, Address, and Command (0011b or 0111b). If the upper 24 bits on the address bus match IOAR (for I/O reads) or MEM (for memory reads), the RTL8169SB(L) will generate DEVSELB 2 clock cycles later. On the 2nd cycle after the assertion of DEVSELB, the device will monitor the IRDYB signal. If IRDYB is asserted at that time, the RTL8169SB(L) will assert TRDYB. On the next clock the 32-bit double word will be latched in, and TRDYB will be forced HIGH for 1 cycle and then tri-stated. Target write operations must be 32-bits wide. If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8169SB(L) will still latch the first double word as described above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted. Figure 5. Target Write Operation Integrated Gigabit Ethernet Controller (NIC) 13 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.2.3. Master Read A Master Read operation starts with the RTL8169SB(L) asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB, Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3 cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB. The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will issue a master abort by asserting FRAMEB HIGH for 1 cycle, and IRDYB will be forced HIGH on the following cycle. Both signals will become tri-state on the cycle following their deassertion. On the clock edge after the generation of Address and Command, the address bus will become tri-state, and the C/BE bus will contain valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be deasserted if this is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, data will be latched in (and the byte enables will change if necessary). This will continue until the cycle following the deassertion of FRAMEB. On the clock where the second to last read cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On the next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It too will be tri-stated 1 cycle later. This will conclude the read operation. The RTL8169SB(L) will never force a wait state during a read operation. Figure 6. Master Read Operation Integrated Gigabit Ethernet Controller (NIC) 14 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.2.4. Master Write A Master Write operation starts with the RTL8169SB(L) asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB, Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3 cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB. The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will issue a Master Abort by asserting FRAMEB HIGH for 1 cycle. IRDYB will be forced HIGH on the following cycle. Both signals will become tri-state on the cycle following their deassertion. On the clock edge after the generation of Address and Command, the data bus will become valid, and the C/BE bus will contain valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be deasserted if this is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, valid data for the next cycle will become available (and the byte enables will change if necessary). This will continue until the cycle following the deassertion of FRAMEB. On the clock where the second to last write cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On the next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It too will be tri-stated 1 cycle later. This will conclude the write operation. The RTL8169SB(L) will never force a wait state during a write operation. Figure 7. Master Write Operation Integrated Gigabit Ethernet Controller (NIC) 15 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.2.5. Configuration Access Configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated by the system. For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Command (1010b or 1011b) during the Address phase. The RTL8169SB(L) will respond as it does during Target operations. Configuration reads must be 32-bits wide, but writes may access individual bytes. Integrated Gigabit Ethernet Controller (NIC) 16 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.3. LED Functions The RTL8169SB(L) supports 4 LED signals in 4 different configurable operation modes. The following sections describe the different LED actions. 6.3.1. Link Monitor The Link Monitor senses the link integrity or if a station is down, such as LINK10, LINK100, LINK1000, LINK10/100/1000, LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no network connection exists. 6.3.2. Rx LED In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. Power On LED = High Receiving Packet? Yes No LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 8. Rx LED Integrated Gigabit Ethernet Controller (NIC) 17 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.3.3. Tx LED In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Power On LED = High Transmitting Packet? Yes No LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 9. Tx LED Integrated Gigabit Ethernet Controller (NIC) 18 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.3.4. Tx/Rx LED In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring. Power On LED = High Tx/Rx Packet? Yes No LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 10. Tx/Rx LED Integrated Gigabit Ethernet Controller (NIC) 19 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.3.5. LINK/ACT LED In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8169SB(L) is linked and operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Power On LED = High Link? Yes LED = Low No No Tx/Rx packet? Yes LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms Figure 11. LINK/ACT LED Integrated Gigabit Ethernet Controller (NIC) 20 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.4. PHY Transceiver 6.4.1. PHY Transmitter In 10Mbps mode, the Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through the transmitting physical layer interface. The transmit 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. Then, the 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the DAC converter. In 100Mbps mode, the transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code via 4B/5B coding technology, scrambling, and serializing before being converted to 125MHz NRZ and NRZI signals. After that, the NRZI signal is passed to the MLT-3 encoder, then to the DAC converter for transmission onto the media. In 1000Mbps mode, the RTL8169SB(L)'s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. Then those code groups are passed through a waveform shaping filter to minimize EMI effects, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a DAC. 6.4.2. PHY Receiver In MII (10Mbps) mode, the received differential signal is converted into a Manchester-encoded data stream. The stream is processed with a Manchester decoder, and is de-serialized into 4-bit wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz. In 100Mbps mode, the MLT-3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT-3 and NRZI decoder, descrambler, 4B/5B decoder, and then is presented to the MII interface in 4-bit wide nibbles at a clock speed of 25MHz. In GMII mode, the input signal from the media first passes through the on-chip sophisticated hybrid circuit to subtract the transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received signal is processed with adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. Then the 8-bit wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager. Integrated Gigabit Ethernet Controller (NIC) 21 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.5. Next Page If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and Reg8 as defined in IEEE 802.3ab. 6.6. EEPROM Interface The RTL8169SB(L) requires the attachment of an external EEPROM. The 93C46 is a 1K-bit EEPROM (the 93C56 is a 2K-bit EEPROM, the 93C66 is a 4K-bit EEPROM). The EEPROM interface provides the ability for the RTL8169SB(L) to read from and write data to an external serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a power-on or software EEPROM auto-load command. The RTL8169SB(L) will auto-load values from the EEPROM. If the EEPROM is not present, the RTL8169SB(L) initialization uses default values for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM using bit-bang accesses via the 9346CR Register, or using PCI VPD. The interface consists of EESK, EECS, EEDO, and EEDI. Table 10. EEPROM Interface EEPROM EECS EESK EEDI/Aux Description 93C46 (93C56/93C66) chip select. EEPROM serial data clock. Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on. This pin should be connected to Boot PROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8169SB(L) assumes that no Aux. Power exists. Output data bus EEDO Integrated Gigabit Ethernet Controller (NIC) 22 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 6.7. Power Management The RTL8169SB(L) is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-Directed Power Management (OSPM) environment. The RTL8169SB(L) can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via PME# when such a packet or event occurs. Then, the whole system can be restored to a normal state to process incoming jobs. When the RTL8169SB(L) is in power down mode (D1 ~ D3): * The Rx state machine is stopped, and the RTL8169SB(L) monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8169SB(L) will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO buffer. The FIFO status and packets that have already been received into the Rx FIFO before entering power down mode are held by the RTL8169SB(L). Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held. After restoration to a D0 state, the RTL8169SB(L) transfers data that was not moved into the Tx FIFO buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. * * * The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0's. Example: If EEPROM D3c_support_PME = 1: * * If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7) If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0's (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value). Integrated Gigabit Ethernet Controller (NIC) 23 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet If EEPROM D3c_support_PME = 0: * * If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77) If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0's (if EEPROM PMC = C2 77, then PCI PMC = 02 76) In the above case, if wakeup support is not desired when main power is off, it is suggested that the EEPROM PMC be set to 02 76. Link Wakeup occurs only when the following conditions are met: * The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met: * * * * The destination address of the received Magic Packet is acceptable to the RTL8169SB(L), e.g. a broadcast, multicast, or unicast packet addressed to the current RTL8169SB(L) adapter. The received Magic Packet does not contain a CRC error. The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in the current power state. The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid (Fast) Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met: * * * * The destination address of the received Wakeup Frame is acceptable to the RTL8169SB(L), e.g. a broadcast, multicast, or unicast address to the current RTL8169SB(L) adapter. The received Wakeup Frame does not contain a CRC error. The PMEn bit (CONFIG1#0) is set to 1. The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC* of the sample Wakeup Frame pattern given by the local machine's OS. Or, the RTL8169SB(L) is configured to allow direct packet wakeup, e.g. a broadcast, multicast, or unicast network packet. *16-bit CRC: The RTL8169SB(L) supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). Integrated Gigabit Ethernet Controller (NIC) 24 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet The PME# signal is asserted only when the following conditions are met: * * * * * The PMEn bit (bit0, CONFIG1) is set to 1. The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1. The RTL8169SB(L) may assert PME# in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space. A Magic Packet, LinkUp, or Wakeup Frame has been received. Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8169SB(L) to stop asserting a PME# (if enabled). When the device is in power down mode, e.g. D1-D3, the IO, MEM, and Boot ROM spaces are all disabled. After a RST# assertion, the device's power state is restored to D0 automatically if the original power state was D3cold. There is no hardware delay at the device's power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required. The RTL8169SB(L) also supports the legacy LAN WAKE-UP function. The LWAKE pin is used to notify legacy motherboards to execute the wake-up process whenever the device receives a wakeup event, such as Magic Packet. The LWAKE signal is asserted according to the following settings: 1. LWPME bit (bit4, CONFIG4): * * LWAKE can only be asserted when PMEB is asserted and ISOLATEB is low. LWAKE is asserted whenever a wakeup event occurs. 2. Bit1 of DELAY byte (offset 1Fh, EEPROM): * * LWAKE signal is enabled. LWAKE signal is disabled. Integrated Gigabit Ethernet Controller (NIC) 25 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 7. Characteristics 7.1. Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified. Table 11. Absolute Maximum Ratings Description/Symbol Supply Voltage (VDD33, AVDDH) Supply Voltage (AVDDL) Supply Voltage (VDD12, VDD12A) Input Voltage (DCinput) Output Voltage (DCoutput) Storage Temperature Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -55 Maximum 4 3 1.5 VDD33 + 0.5 VDD33 + 0.5 +125 Unit V V V V V C 7.2. Recommended Operating Conditions Table 12. Recommended Operating Conditions Description Supply Voltage VDD Pins VDD33, AVDDH AVDDL VDD12, VDD12A Minimum 3.0 2. 32 1.13 0 Typical 3.3 2.5 1.2 Maximum 3.6 2.67 1.28 70 125 Unit V V V C C Ambient Temperature TA Maximum Junction Temperature 7.3. Crystal Requirements Table 13. Crystal Requirements Symbol Fref Fref Stability Fref Tolerance Description/Condition Parallel resonant crystal reference frequency, fundamental mode, AT-cut type. Parallel resonant crystal frequency stability, fundamental mode, AT-cut type. Ta=25C. Parallel resonant crystal frequency tolerance, fundamental mode, AT-cut type. Ta=-20C ~+70C. 26 Minimum Typical 25 Maximum Unit MHz ppm ppm -50 -30 +50 +30 Integrated Gigabit Ethernet Controller (NIC) Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet Symbol Fref Duty Cycle CL ESR DL Description/Condition Reference clock input duty cycle Load Capacitance Equivalent Series Resistance Drive Level Minimum 40 Typical Maximum 60 27 10 0.5 Unit % pF mW 7.4. Thermal Characteristics Table 14. Thermal Characteristics Parameter Storage temperature Operating temperature Minimum -55 0 Maximum +125 70 Units C C 7.5. DC Characteristics Table 15. DC Characteristics Symbol VDD33 AVDDL VDD12, VDD12A Voh Vol Vih Vil Iin Ioz Icc33 Parameter 3.3V Supply Voltage 2.5V Supply Voltage 1.2V Supply Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Tri-State Output Leakage Current Average Operating Supply Current from 3.3V Average Operating Supply Current from 1.2V Ioh = -8mA Iol = 8mA 0.5 * VDD33 -0.5 Vin =VDD33 or GND Vout =VDD33 or GND -1.0 Conditions Minimum 3.0 2.32 1.13 0.9 * VDD33 Typical 3.3 2.5 1.2 Maximum 3.6 2.67 1.28 VDD33 0.1 * VDD33 VDD33+0.5 0.3 * VDD33 1.0 Units V V V V V V V uA -10 10 uA TBD mA Icc12 TBD mA Integrated Gigabit Ethernet Controller (NIC) 27 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 7.6. AC Characteristics 7.6.1. Serial EEPROM Interface Timing 93C46(64*16)/93C56(128*16)/93C66(256*16) EESK EECS EEDI (Read) (Read) tcs 1 1 0 An A2 A1 A0 0 Dn D1 D0 EEDO High Impedance EESK EECS EEDI (Write) (Write) tcs 1 0 1 An ... A0 Dn ... D0 BUSY twp READY EEDO High Impedance tsk EESK tskh tskl tcsh EECS EEDI tcss tdis tdih tdos tdoh EEDO EEDO (Read) tsv (Program) STATUS VALID Figure 12. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters Symbol tcs twp tsk tskh tskl Parameter Minimum CS Low Time Write Cycle Time SK Clock Cycle Time SK High Time SK Low Time EEPROM Type 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 28 Min. 1000/250 4/1 1000/500 1000/250 Max. 10/10 Unit ns ms s ns ns Rev. 1.5 Integrated Gigabit Ethernet Controller (NIC) Track ID: JATR-1076-21 RTL8169SB(L) Datasheet Symbol tcss tcsh tdis tdih tdos tdoh tsv Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time DO Setup Time DO Hold Time CS to Status Valid EEPROM Type 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) 9346/9356(9366) Min. 200/50 0/0 400/50 400/100 2000/500 Max. Unit ns ns ns ns ns ns ns 2000/500 1000/500 7.7. PCI Bus Operation Timing 7.7.1. PCI Bus Timing Parameters Table 17. PCI Bus Timing Parameters 66MHz Symbol T val T val(ptp) T on T off T su T su(ptp) Th T rst T rst-clk T rst-off T rhfa T rhff Parameter CLK to Signal Valid Delay-bused signals CLK to Signal Valid Delay-point to point Float to Active Delay Active to Float Delay Input Setup Time to CLK-bused signals Input Setup Time to CLK-point to point Input Hold Time from CLK Reset active time after power stable Reset active time after CLK STABLE Reset Active to Output Float delay RSTB High to First configuration Access RSTB High to First FRAMEB assertion Min 2 2 2 14 3 5 0 1 100 40 2^25 5 2^25 5 7 10 0 1 100 40 Max 6 6 Min 2 2 2 28 33MHz Symbol 11 12 Parameter ns ns ns ns ns ns ns ms s ns clocks clocks Integrated Gigabit Ethernet Controller (NIC) 29 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet V_th CLK V_test T_val V_tl V_trise, V_tfall OUTPUT DELAY Tri-State OUTPUT V_test T_on T_off V_test Figure 13. Output Timing Measurement Conditions V_th CLK V_th T_su V_test V_tl V_test T_h V_test V_tl V_max INPUT inputs valid Figure 14. Input Timing Measurement Conditions Table 18. Measurement Condition Parameters Symbol Vth Vtf Vtest Vtrise Vtfall Vmax Input Signal Edge Rate Level 0.6Vcc 0.2Vcc 0.4Vcc 0.285Vcc 0.615Vcc 0.4Vcc 1 Units V V V V V V V/ns Integrated Gigabit Ethernet Controller (NIC) 30 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 7.7.2. PCI Clock Specification T_high 0.6Vcc T_low 0.5Vcc 0.4Vcc 0.3Vcc 0.2Vcc T_cyc 0.4Vcc, peak-to-peak (minimum) Figure 15. 3.3V Clock Waveform V_ih CLK (@ Device #1) V_il T_skew V_test T_skew V_ih V_test V_il T_skew CLK (@ Device #2) Figure 16. Clock Skew Diagram Table 19. Clock and Reset Specifications 66MHz Symbol Tcyc Thigh Tlow --Tskew Parameter CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate RST# Slew Rate CLK Skew Min 15 6 6 1.5 50 Max 30 Min 30 11 11 1 50 33MHz Symbol Parameter ns ns ns V/ns mV/ns ns 4 1 4 2 Integrated Gigabit Ethernet Controller (NIC) 31 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 7.7.3. PCI Transactions CLK 1 2 3 4 5 6 7 8 9 10 FRAMEB AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Figure 17. I/O Read CLK 1 2 3 4 5 6 7 8 9 10 FRAMEB AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Figure 18. I/O Write Integrated Gigabit Ethernet Controller (NIC) 32 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet CLK 1 2 3 4 5 6 7 8 9 10 FRAMEB IDSEL AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Figure 19. Configuration Read CLK 1 2 3 4 5 6 7 8 9 10 FRAMEB IDSEL AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Figure 20. Configuration Write Integrated Gigabit Ethernet Controller (NIC) 33 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet CLK 1 2 3 4 5 6 7 8 9 10 REQB-A REQB-B GNTB-A GNTB-B FRAMEB AD ADDRESS DATA ADDRESS DATA Figure 21. Bus Arbitration CLK 1 2 3 4 5 6 7 8 9 FRAMEB AD31-0 ADDRESS DATA-1 DATA-2 DATA-3 C/BE3-0B BUS CMD DATA TRANSFER BE3-0B DATA TRANSFER WAIT DATA TRANSFER IRDYB WAIT TRDYB DEVSELB Figure 22. Memory Read Below 4GB Integrated Gigabit Ethernet Controller (NIC) 34 WAIT Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet CLK 1 2 3 4 5 6 7 8 9 FRAMEB AD31-0 ADDRESS DATA-1 DATA-2 DATA-3 C/BE3-0B BUS CMD BE3-0B-1 BE3-0B-2 DATA TRANSFER DATA TRANSFER BE3-0B-3 DATA TRANSFER IRDYB WAIT WAIT TRDYB DEVSELB Figure 23. Memory Write Below 4GB CLK 1 2 3 4 5 6 7 8 9 FRAMEB IRDYB TRDYB STOPB DEVSELB Figure 24. Target Initiated Termination - Disconnect Integrated Gigabit Ethernet Controller (NIC) 35 WAIT Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet CLK 1 2 3 4 5 6 7 8 9 FRAMEB IRDYB TRDYB STOPB DEVSELB Figure 25. Target Initiated Termination - Abort CLK 1 2 3 4 5 6 7 8 9 FRAMEB IRDYB TRDYB NO RESPONSE ACKNOWLEDGE DEVSELB FAST MED SLOW SUB Figure 26. Master Initiated Termination - Abort Integrated Gigabit Ethernet Controller (NIC) 36 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet CLK 1 2 3 4 5 6 7 8 9 1 0 FRAMEB AD ADDRESS DATA ADDRESS DATA C/BE# BUS CMD BE# BUS CMD BE# PAR/PAR64 SERR# PERR# Figure 27. Parity Operation - One Example Integrated Gigabit Ethernet Controller (NIC) 37 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet CLK 1 2 3 4 5 6 7 8 9 10 FRAMEB AD31-0 LO-ADDR HI-ADDR DATA-1 DATA-2 DATA-3 C/BE3-0B DAC CMD BUS CMD DATA TRANSFER BE3-0B DATA TRANSFER WAIT DATA TRANSFER IRDYB WAIT TRDYB DEVSELB Figure 28. Memory Read Above 4GB (DAC) CLK 1 2 3 4 5 6 7 8 9 10 FRAMEB AD31-0 LO-ADDR HI-ADDR DATA-1 DATA-2 WAIT DATA-3 C/BE3-0B DAC CMD BUS CMD BE3-0B-1 BE3-0B-2 DATA TRANSFER DATA TRANSFER BE3-0B-3 DATA TRANSFER IRDYB WAIT WAIT TRDYB DEVSELB Figure 29. Memory Write Above 4GB (DAC) Integrated Gigabit Ethernet Controller (NIC) 38 Track ID: JATR-1076-21 WAIT Rev. 1.5 RTL8169SB(L) Datasheet 8. Mechanical Dimensions 8.1. 128-Pin QFP Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Integrated Gigabit Ethernet Controller (NIC) 39 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 8.2. Notes for 128-Pin QFP Dimensions Symbol Dimensions in inches Min A A1 A2 b c D E e Dimensions in mm Min 0.10 2.60 0.12 0.05 13.75 19.75 0.25 16.90 22.90 0.68 1.35 0 Typical 0.25 2.85 0.22 0.15 14.00 20.00 0.5 17.20 23.20 0.88 1.60 Max 3.40 0.91 3.10 0.32 0.25 14.25 20.25 0.75 17.50 23.50 1.08 1.85 0.10 12 Notes: 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. Should be based on final visual inspection. Typical 0.010 0.112 0.009 0.006 0.551 0.787 0.020 0.677 0.913 0.035 0.063 - Max 0.134 0.036 0.122 0.013 0.010 0.561 0.797 0.030 0.689 0.925 0.043 0.073 0.004 12 0.004 0.102 0.005 0.002 0.541 0.778 0.010 0.665 0.902 0.027 0.053 0 TITLE: 128 QFP (14x20 mm) PACKAGE OUTLINE -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL APPROVE DOC. NO. VERSION PAGE CHECK DWG NO. DATE Q128 - 1 HD HE L L1 y REALTEK SEMICONDUCTOR CORP. Integrated Gigabit Ethernet Controller (NIC) 40 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 8.3. 128-Pin LQFP Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Integrated Gigabit Ethernet Controller (NIC) 41 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 8.4. Notes for 128-Pin LQFP Dimensions Symbol Dimension in inch Min A A1 0.000 Type 0.004 Max 0.067 0.008 Dimension in mm Min 0.00 Type Max 1.70 0.25 Notes: 1.Dimension b does not include dambar protrusion/intrusion. 2.Controlling dimension: Millimeter 3. General appearance spec. Should be based on final visual inspection. A2 b c 0.051 0.006 0.004 0.055 0.009 - 0.059 0.011 0.006 1.30 0.15 0.09 1.40 0.22 - 1.50 0.29 0.20 TITLE: 128LD LQFP ( 14x20x1.4 mm*2 ) PACKAGE OUTLINE D E e 0.541 0.778 0.551 0.787 0.020 0.561 13.75 0.797 19.75 BSC 0.640 15.90 0.877 21.70 0.031 REF 9 0 0.45 14.00 20.00 0.50 16.00 22.00 0.60 1.00 3.5 14.25 20.25 BSC 16.30 23.30 0.75 REF 9 CHECK APPROVE CU L/F, FOOTPRINT 2.0 mm LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. DATE LQ128 - 1 HD HE L L1 0.620 0.855 0.016 0.630 0.866 0.024 0.039 0 3.5 REALTEK SEMICONDUCTOR CORP. Integrated Gigabit Ethernet Controller (NIC) 42 Track ID: JATR-1076-21 Rev. 1.5 RTL8169SB(L) Datasheet 9. Ordering Information Table 20. Ordering Information Part number RTL8169SB RTL8169SBL RTL8169SB-LF RTL8169SBL-LF Package 128-pin QFP 128-pin LQFP 128-pin QFP 128-pin LQFP Status Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw Integrated Gigabit Ethernet Controller (NIC) 43 Track ID: JATR-1076-21 Rev. 1.5 |
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